¹College of Computer, National University of Defense Technology, 410073, Changsha, Hunan, China.
²Department of Electronic Systems, KTH-Royal Institute of Technology, 16440 Kista, Stockholm, Sweden.
³Institute of Computer Technology, Vienna University of Technology, 1040 Vienna, Austria.

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Abstract—Technology advance enables integration of a lot of resources on multi-core Network-on-Chips (NoCs). In such complex system, memories are preferably distributed and supporting Distributed Shared Memory (DSM) is essential for the sake of re-using huge amount of legacy code and easy programming. Besides, the design complexity of multi-core NoCs results in long time-to-market and high cost. Motivated by these two considerations, we propose a hardware/software co-design, called “command-triggered microcode execution”. It guides a Dual Microcode Controller (DMC) to look for a flexible DSM support under multi-core NoCs. This paper describes hardware/software co-operation, command type, work model, work flow and microprogramming development flow in our proposed hardware/software co-design. Microcodes of basic DSM functions are implemented and their performance evaluations are discussed. Experimental results show that, when the system size is scaled up, the delay overhead incurred by the DMC may become less significant in comparison to the network delay. In this way, the delay efficiency of our hardware/software co-design is close to that of hardware solutions on average but our co-design still has all the flexibility of software solutions.

Index Terms—Command, microcode, microprogramming, hardware/software co-design, distributed shared memory, multi-core network-on-chips.

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Cite: Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen, Man Liao, "Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips," Journal of Software vol. 10, no. 2, pp. 142-161, 2015.