Volume 2 Number 5 (Nov. 2007)
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JSW 2007 Vol.2(5): 52-63 ISSN: 1796-217X
doi: 10.4304/jsw.2.5.52-63

Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware

Vaclav Dvorak
Brno University of Technology, Brno, Czech Republic

Abstract—The paper addresses software and firmware implementation of multiple-output Boolean functions based on cascades of Look-Up Tables (LUTs). A LUT cascade is described as a means of compact representation of a large class of sparse Boolean functions, evaluation of which then reduces to multiple indirect memory accesses. The method is compared to a technique of direct PLA emulation and is illustrated on examples. A specialized micro-engine is proposed for even faster evaluation than is possible with universal microprocessors. The presented method is flexible in making trade-offs between performance and memory footprint and may be useful for embedded applications where the processing speed is not critical. Evaluation may run on various CPUs and DSP cores or slightly faster on FPGA-based micro-programmed controllers.

Index Terms—Embedded software, Boolean function evaluation, Binary Decision Diagrams, LUT cascades

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Cite: Vaclav Dvorak, " DEfficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware," Journal of Software vol. 2, no. 5, pp. 52-63, 2007.

General Information

ISSN: 1796-217X (Online)
Frequency: Monthly (2006-2019); Bimonthly (Since 2020)
Editor-in-Chief: Prof. Antanas Verikas
Executive Editor: Ms. Yoyo Y. Zhou
Abstracting/ Indexing: DBLP, EBSCO, Google Scholar, ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat, etc
E-mail: jsw@iap.org
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