¹Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 8080135, Japan
²Sony LSI Design Inc., Yokohama, 2400005, Japan
³Information and Media Processing Research Laboratories, NEC Corp., Kawasaki, 2118666, Japan

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Abstract—Power analysis attacks are based on analyzing the power consumption of the cryptographic devices while they perform the encryption operation. Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. It has been one of the effective side channel attacks that threaten the security of CMOS circuits. However, few works consider the leakage of glitches at the logic gates. In this paper, we present a new power consumption model, namely Switching Glitch (SG) power leakage model, which not only considers the data dependent switching activities but also including glitch power consumptions in CMOS circuits. Additionally, from a theoretical point of view, we show how to estimate the glitch factor. The experiments against AES implementation validate the proposed model. Compared with CPA based on Hamming Distance model, the power traces of recovering keys have been decreased by as much as 28.9%.

Index Terms—side channel attacks, correlation power analysis (CPA), glitches, AES, Hamming Distance.

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Cite: Hongying Liu, Guoyu Qian, Yukiyasu Tsunoo, Satoshi Goto, "The Switching Glitch Power Leakage Model," Journal of Software vol. 6, no. 9, pp. 1787-1794, 2011.