doi: 10.4304/jsw.6.9.1787-1794
The Switching Glitch Power Leakage Model
- 1 Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 8080135, Japan
- 2 Sony LSI Design Inc., Yokohama, 2400005, Japan
- 3 Information and Media Processing Research Laboratories, NEC Corp., Kawasaki, 2118666, Japan
Abstract
Power analysis attacks are based on analyzing the power consumption of the cryptographic devices while they perform the encryption operation. Correlation Power Analysis (CPA) attacks exploit the linear relation between the known power consumption and the predicted power consumption of cryptographic devices to recover keys. It has been one of the effective side channel attacks that threaten the security of CMOS circuits. However, few works consider the leakage of glitches at the logic gates. In this paper, we present a new power consumption model, namely Switching Glitch (SG) power leakage model, which not only considers the data dependent switching activities but also including glitch power consumptions in CMOS circuits. Additionally, from a theoretical point of view, we show how to estimate the glitch factor. The experiments against AES implementation validate the proposed model. Compared with CPA based on Hamming Distance model, the power traces of recovering keys have been decreased by as much as 28.9%.
Keywords
- side channel attacks
- correlation power
How to Cite
Hongying Liu, Guoyu Qian, Yukiyasu Tsunoo, and Satoshi Goto, "The Switching Glitch Power Leakage Model," Journal of Software, vol. 6, no. 9, pp. 1787-1794, 2011. https://doi.org/ 10.4304/jsw.6.9.1787-1794
Copyright & License
Copyright © 2011 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).