Volume 4 Number 1 (Feb. 2009)
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JSW 2009 Vol.4(1): 81-89 ISSN: 1796-217X
doi: 10.4304/jsw.4.1.81-89

Loop Kernel Pipelining Mapping onto Coarse- Grained Reconfigurable Architecture for Data- Intensive Applications

Dawei Wang, Sikun Li, and Yong Dou
College of Computer Science, University of Defense Technology, Changsha, P.R.China

Abstract—Coarse-grained reconfigurable architectures (CGRA) provide flexible and efficient solution for data-intensive applications. Loop kernels of these applications always consume much execution time of the whole program. However, mapping loop kernels onto CGRA is still hard to meet performance/cost constraints. This paper proposes a novel approach for automatically mapping loop kernels onto CGRA with loop selfpipelining to optimize data-intensive applications. The problem formulation is shown first. Then we present the resource sharing and pipelining of lspCGRA, together with its template standard. Further, a loop kernel pipelining mapping is proposed. The conclusions show that our approach gains less resource occupation by 16.3% and more throughputs by 169.1% than previous advanced SPKM.

Index Terms—Reconfigurable computing, loop self-pipelining, data-intensive application, design decision

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Cite: Dawei Wang, Sikun Li, and Yong Dou, "Loop Kernel Pipelining Mapping onto Coarse- Grained Reconfigurable Architecture for Data- Intensive Applications," Journal of Software vol. 4, no. 1, pp. 81-89, 2009.

General Information

ISSN: 1796-217X (Online)
Frequency: Monthly (2006-2019); Bimonthly (Since 2020)
Editor-in-Chief: Prof. Antanas Verikas
Executive Editor: Ms. Yoyo Y. Zhou
Abstracting/ Indexing: DBLP, EBSCO, ProQuest, INSPEC, ULRICH's Periodicals Directory, WorldCat, etc
E-mail: jsw@iap.org
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